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[Data structs] hdl

Description: 对lvds的结构用verilog和vhdl代码进行了详细的描述-The structure of the lvds with verilog and vhdl code described in detail
Platform: | Size: 21504 | Author: LUCAS | Hits:

[VHDL-FPGA-Verilog] Verilog_HDl_Code

Description: 《精通Verilog HDL语言编程》中的Verilog实例源码-Verilog HDL Code
Platform: | Size: 28672 | Author: 李成军 | Hits:

[VHDL-FPGA-Verilog] Move071221133_32

Description: 用Verilog HDL语言或VHDL语言来编写，实现32位的桶形移位器。 并在Quartus Ⅱ上实现模拟仿真；-With the Verilog HDL language or VHDL language to write to achieve 32-bit barrel shifter. To achieve in the Quartus Ⅱ simulation
Platform: | Size: 818176 | Author: 于伟 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Platform: | Size: 984064 | Author: Stone Lei | Hits:

[VHDL-FPGA-Verilog] DHT22_v1.1

Description: 我以前曾发过V1.0版的，这是此版的修正版v1.1,修正了以前版本中的一个错误，即只能读一个数据后就再也读不出温度数据的错误。 这个是用Quartus II软件写的Verilog HDL语言写的与温湿度传感器DHT2x通信的代码. 里面有详细的注解. 主要用于DHT2x单线总线通信转换为8位并行总线通信,应用于具有外部8位总线访问功能的单片机直接读取温湿度数据. 此程序在EPM7128SLC-10中成功测试. -I' ve once spoke V1.0 version, which is a modified version of this edition v1.1, fixes a bug in previous versions, that is no longer only after reading a data temperature data could not be read errors. This is done using Quartus II software, written in Verilog HDL language written with the temperature and humidity sensor DHT2x communications code. Which detailed footnotes. DHT2x mainly used for single-wire bus communication is converted to 8-bit parallel bus communication, used with an external 8-bit bus MCU read directly access features temperature and humidity data. EPM7128SLC-10 in this program successfully tested.
Platform: | Size: 1094656 | Author: yuantielei | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[VHDL-FPGA-Verilog] verilogdct

Description: dct实现verilog hdl的数字图像处理，源代码-dct achieve verilog hdl digital image processing, source code
Platform: | Size: 28672 | Author: xutongxue | Hits:

[VHDL-FPGA-Verilog] ds18b20s4

Description: 四路DS18B20的verilog HDL 代码，精度为1℃无须转换数据，根据输入地址改变直接输出结果。占用600个LE资源，相对于单路程序，更为精减-Four DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, enter the address change in accordance with the direct output. Occupy 600 LE resources, as opposed to one-way process, a more streamlined
Platform: | Size: 443392 | Author: chenwl | Hits:

[Communication-Mobile] delayandGMSKdemod

Description: GSM中，GMSK解调与延迟程序，Verilog HDL。-GMSK DEMOD
Platform: | Size: 3048448 | Author: 杜晓明 | Hits:

[VHDL-FPGA-Verilog] Verilog_Coding_Style_Proposal

Description: Altera公司的Verilog HDL 代码编写规范-Altera Verilog HDL code style for the proposed specification
Platform: | Size: 1850368 | Author: 张永杰 | Hits:

[VHDL-FPGA-Verilog] dwt2d_latest[1].tar

Description: 小波变换的开源代码（Verilog HDL）包括有测试文件，本人看过，挺好。-code of dwt
Platform: | Size: 413696 | Author: 陈先生 | Hits:

[VHDL-FPGA-Verilog] TLC5620

Description: Verilog HDL语言，FPGA实现TLC5620的DAC源代码-Verilog HDL language, FPGA implementation of the DAC TLC5620 source code
Platform: | Size: 496640 | Author: 双目林 | Hits:

[VHDL-FPGA-Verilog] Desktop

Description: 用verilog HDL编写的多路选择器的代码，包括一部分延迟-Prepared using verilog HDL code MUX, including part of the delay
Platform: | Size: 16384 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] ca_gen

Description: 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number, the output generated C/A code. This procedure carried out in the code optimization, take up fewer resources.
Platform: | Size: 1024 | Author: 李殿为 | Hits:

[VHDL-FPGA-Verilog] DE2_70_AUDIO

Description: 是用VERILOG HDL和NIOS II C/C++ 编的DE2-70板子的音频编解码芯片的使用工程-Is VERILOG HDL and NIOS II C/C++ code of the DE2-70 board in the audio codec chip, the use of project
Platform: | Size: 21566464 | Author: 覃建策 | Hits:

[Other] huaweiVerilogHDL

Description: 华为_Verilog HDL入门教程（pdf），主要介绍了Verilog HDL 语言的一些基本知识，目的是使初学者能够迅速掌握HDL设计方法，初步了解并掌握Verilog HDL语言的基本要素，能够读懂简单的设计代码并能 够进行一些简单设计的Verilog HDL建模。-Huawei _Verilog HDL Tutorial pdf version mainly introduces the Verilog HDL language, some basic knowledge, the purpose is to enable beginners to quickly master the HDL design method, initially to understand and master the basic elements of Verilog HDL language, can read simple design code and be able to carry out some simple design of the Verilog HDL modeling.
Platform: | Size: 263168 | Author: 张三丰 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA应用开发入门与典型实例 代码 FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。 -FPGA Application Development and Typical examples of code for FPGA (field programmable logic device) for its small size, low power consumption, high stability, the advantages are widely used in the design of electronic products. This book comprehensively explained the background FPGA system design, hardware design, hardware description language Verilog HDL syntax and basic common statement, FPGA use of the software development tools, FPGA-based soft-core embedded systems, FPGA design of the basic principles , skills, IP core, FPGA interface design field in a typical application, FPGA+ DSP system design and debug, and digital zoom systems and PCI data acquisition system design of two cases of complete system.
Platform: | Size: 10980352 | Author: 海到无涯 | Hits:

[File Format] code_style

Description: verilog HDL code addtional style for user.
Platform: | Size: 18432 | Author: 凄凄 | Hits:

[Other] DE2_NIOS_HOST_MOUSE_VGA

Description: 显示控制电路是整个场序彩色显示【15】【16】系统的心设计部分,本文采用Verilog HDL来设计。首先编写对各单元电路进行以行为级描述的Verilog代码,再用EDA工具对Verilog HDL代码进行功能仿真和逻辑综合。-Display control circuit is the field sequential color display 【15】 【16】 system design part of the heart, this paper Verilog HDL to design. First of all write circuits of each unit described in behavioral Verilog code, and then EDA tools on the Verilog HDL code for functional simulation and logic synthesis.
Platform: | Size: 4121600 | Author: 王朔 | Hits:

[VHDL-FPGA-Verilog] 8250

Description: Verilog HDL写的串行接口控制器82-Written in Verilog HDL serial interface controller 8255
Platform: | Size: 407552 | Author: anqi | Hits:
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